We’re looking for an FPGA Design Engineer for our next-generation satellite modules who has experience with digital logic design (Verilog or VHDL), ideally in the field of digital signal processing and has knowledge in digital verification.
The ideal candidate will also be familiar with back end digital design flow – constraining and running a design through synthesis and implementation.
Role
- Design reusable RTL blocks
- Update and Integrate IP blocks into existing designs
- Set up testing frameworks for new or existing RTL IP/library blocks
- Constrain digital designs and analyze timing and power performance
- Integrate and test RTL designs on evaluation and custom hardware
Essential requirements
- Electronics and/or Electrical Engineering Degree (at least Bachelor or similar)
- Minimum 2 years of digital design/verification experience (ASIC or FPGA)
- Good understanding of the full digital design flow (Design, verification, synthesis and PnR)
- Knowledge of Verilog or VHDL (Both is an advantage)
- Experience in designing multi-clock domain logic
Requirements considered an advantage
- Knowledge of the DVB-S2X and/or CCSDS communication standards
- Experience with using the Vivado IDE
- Experience with embedded Linux
- Experience with some standardized verification framework (e.g UVM)
Personal skills
- Open to knowledge sharing
- Understanding the importance of the last mile delivery
- Quick learner, proactive, ready to work on his/her own and in a team
- Excellent communication skills and positive attitude
- Ability to manage multiple priorities at the same time